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| M48Z30 M48Z30Y CMOS 32K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x 8 SRAMs AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION CHOICE of TWO WRITE PROTECT VOLTAGES: - M48Z30: 4.5V VPFD 4.75V - M48Z30Y: 4.2V VPFD 4.50V BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED 28 1 PMDIP28 (PM) Module Figure 1. Logic Diagram DESCRIPTION The M48Z30/30Y 32K x 8 ZEROPOWER(R) RAM is a non-volatile 262,144 bit Static RAM organized as 32,768 words by 8 bits. The device combines an internal lithium battery and a full CMOS SRAM in a plastic 28 pin DIP Module. The ZEROPOWER Table 1. Signal Names A0 - A14 DQ0 - DQ7 E G W VCC VSS Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground July 1994 1/12 M48Z30, M48Z30Y Table 2. Absolute Maximum Ratings Symbol TA TSTG TBIAS TSLD VIO VCC Parameter Ambient Operating Temperature Storage Temperature (V CC Off) Temperature Under Bias Lead Soldering Temperature for 10 seconds Input or Output Voltages Supply Voltage Value 0 to 70 -40 to 70 -10 to 70 260 -0.3 to 7 -0.3 to 7 Unit C C C C V V Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode. Table 3. Operating Modes Mode Deselect Write Read Read Deselect Deselect Note: X = VIH or VIL VCC 4.75V to 5.5V or 4.5V to 5.5V E VIH VIL VIL VIL G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode VSO to VPFD (min) VSO X X Figure 2. DIP Pin Connections DESCRIPTION (cont'd) RAM directly replaces industry standard SRAMs. It also fits into many EPROM and EEPROM sockets, providing the nonvolatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The M48Z30/30Y has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately3V, the control circuitry connectsthe battery which sustains data until valid power returns. READ MODE The M48Z30/30Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 262,144 locations in the static storage array. Thus, the unique address 2/12 M48Z30, M48Z30Y Figure 3. Block Diagram specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing that the E and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access Time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until t AVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access. WRITE MODE The M48Z30/30Yis in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. AC MEASUREMENT CONDITIONS Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 4. AC Testing Load Circuit 3/12 M48Z30, M48Z30Y Table 4. Capacitance (1, 2) (TA = 25 C, f = 1 MHz ) Symbol C IN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected Table 5. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) Symbol ILI ILO (1) (1) Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2V Min Max 1 1 85 7 4 Unit A A mA mA mA V V V V ICC ICC1 ICC2 VIL VIH VOL VOH -0.3 2.2 IOL = 2.1mA IOH = -1mA 2.4 0.8 VCC + 0.3 0.4 Note: 1. Outputs deselected. Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C) Symbol VPFD VPFD VSO tDR (2) Parameter Power-fail Deselect Voltage (M48Z30) Power-fail Deselect Voltage (M48Z30Y) Battery Back-up Switchover Voltage Data Retention Time Min 4.5 4.2 Typ 4.6 4.3 3 Max 4.75 4.5 Unit V V V YEARS 10 Notes: 1. All voltages referenced to VSS. 2. @ 25C 4/12 M48Z30, M48Z30Y Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70C) Symbol tF (1) (2) Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time Write Protect Time from VCC = VPFD VSO to VPFD (max) VCC Rise Time E Recovery Time Min 300 10 40 0 40 Max Unit s s tFB tWP tR tER 150 s s 120 ms Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data. Figure 5. Power Down/Up Mode AC Waveforms 5/12 M48Z30, M48Z30Y Table 8. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) M48Z30 / 30Y Symbol Parameter Min tAVAV tAVQV (1) -85 Max Min 100 85 85 45 5 5 40 35 10 10 5 5 -100 Max Unit Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 85 ns 100 100 50 ns ns ns ns ns 40 35 ns ns ns tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ tAXQX (2) (1) Notes: 1. CL = 100pF (see Figure 4). 2. CL = 5pF (see Figure 4) Figure 6. Address Controlled, Read Mode AC Waveforms Note: E = Low, G = Low, W = High. 6/12 M48Z30, M48Z30Y Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms Note: W = High. WRITE MODE (cont'd) A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX or tEHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP , write protection takes place. When Vcc drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z30/30Y after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and Vcc rises above VSO, the battery is disconnected, and the power supply is switched to external Vcc. Write protectioncontinues for tER after VCC reaches VPFD to allow for processor stabilization. After t ER, normal RAM operation can resume. DATA RETENTION MODE With valid VCC applied, the M48Z30/30Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will 7/12 M48Z30, M48Z30Y Table 9. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) M48Z30 / 30Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1,2) -85 Max Min 100 0 0 75 90 5 15 40 40 0 15 35 75 75 5 80 80 5 -100 Max Unit Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 85 0 0 65 75 5 15 35 35 0 15 ns ns ns ns ns ns ns ns ns ns ns 35 ns ns ns ns tAVWH tAVEH tWHQX (1,2) Notes: 1. CL = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low after W going low, the outputs remain in the high-impedance state. 8/12 M48Z30, M48Z30Y Figure 8. Write Enable Controlled, Write AC Waveforms Note: G = High. Figure 9. Chip Enable Controlled, Write AC Waveforms Note: G = High. 9/12 M48Z30, M48Z30Y ORDERING INFORMATION SCHEME Example: M48Z30Y -85 PM 1 Supply Voltage and Write Protect Voltage 30 30Y VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V -85 -100 Speed 85ns 100ns PM Package PMDIP28 Temp. Range 1 0 to 70C For a list of available options (Package and Speed) refer to the current Memory Shortform catalogue. For further information or any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 10/12 M48Z30, M48Z30Y PMDIP28 - 28 pin Plastic DIP Module Symb Typ A A1 B C D E e1 e3 eA L S N PMDIP28 mm Min 9.27 0.38 0.43 0.20 37.34 18.03 2.29 29.72 14.99 3.05 1.91 28 Max 9.52 - 0.59 0.33 38.10 18.80 2.79 36.32 16.00 3.81 2.79 Typ inches Min 0.365 0.015 0.017 0.008 1.470 0.710 0.090 1.170 0.590 0.120 0.075 28 Max 0.375 - 0.023 0.013 1.500 0.740 0.110 1.430 0.630 0.150 0.110 A A1 S B e3 D e1 L eA C N E 1 PMDIP Drawing is not to scale 11/12 M48Z30, M48Z30Y Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved (R) ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics TM BYTEWIDE is a trademark of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 12/12 |
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